Micro-Architecture Design for ARM

Single-cycle / Multi-cycle Processor Design for the ARM ISA in VHDL

This was the course assignment for the Computer Architecture course at IIT Delhi and was meant to give a deep understanding of how processors work and how hardware systems are designed and programmed. We designed and developed the hardware for processing a subset of ARM instruction set in VHDL. We developed single-cycle and multi-cycle designs. We implemented ALU units, Program Memory and Data Memory for the Data path and a Finite-State-Machine for the Control Path to process a subset of the ARM instruction set. We simulated, tested and synthesized the processor.